The present invention relates to a semiconductor structure, and particularly, to an integrated crackstop structure.
In the manufacture of semiconductor devices, a plurality of integrated circuits are simultaneously prepared in a semiconductor wafer through the use of conventional photolithographic techniques. Thus, for example, a wafer may contain multiple separate integrated circuits which have been formed on the substantially planar surface area of the wafer according to conventional techniques. It is also convenient to provide a plurality of secondary devices such as contact pads, test monitor devices, and devices for measurement and alignment on the planar surface adjacent the outer perimeter of each integrated circuit or other semiconductor device. Each single integrated circuit is of relatively minute dimensions so that it is convenient to simultaneously form a plurality of them in a single wafer while marking the boundaries between the individual devices along perpendicular axes referred to as dicing lines or a kerf region. Since the dicing area is a region cut by a metal rotary blade, an element of an IC (hereinafter referred to as a function element) is not formed in this region, but a test element for testing the function element or an alignment mark for mask alignment is often formed there.
In accordance with techniques well known in the art, after a semiconductor wafer has been formed into interconnected semiconductor devices, the chips are tested to identify those which are satisfactory and those improperly formed or malfunctioning and unsatisfactory. As mentioned earlier, it is common practice to put test, measurement, alignment and die seal structures in the kerf region. After testing, adjacent satisfactory chips are left joined together while unsatisfactory chips are separated or the entire wafer is separated and the unsatisfactory chips are discarded. Separation (or dicing) may be performed by conventional techniques such as sawing or laser cutting along the dicing line.
One of the greatest problems of large scale integration is that of obtaining a high enough yield of devices from each wafer to be commercially profitable. As the number and complexity of devices per wafer increases, the yield often decreases proportionally. It is therefore highly desirable to minimize the number of devices that must be discarded as unsatisfactory.
One concern affecting yield is chip package interaction (CPI). A mismatch in the coefficient of thermal expansion between a chip and a laminate may lead to increased stress applied to the chip and result in mechanical damage to the chip. More specifically, the weaker high performance dielectric layers, for example lowK and UltralowK, are susceptible to such mechanical damage. This mechanical damage is detectable using Sonoscan imagery, and appears as a classic “white bump”, with the damage closely affiliated with the solder connection through which the breaking stress is transferred.
White-bump mitigating structural modifications are a subject of considerable interest in today's chip manufacturing environment. Chip package interaction structural modifications may include thicker layers of polymer final passivation material (for example PSPI), which may function as a stress buffer. However, polymer passivation materials tend to have high internal stress, causing wafer bow when applied in thick blanket films. Customized discontinuous structures, such as PSPI Islands or annular bump pads, must be used to reap the benefits of a thick PSPI layer while at the same time limiting wafer bow.
Independently of these concerns, with newer technology nodes, there is a move towards elimination of the industry-standard aluminum pad for cost reduction. The aluminum pad is typically replaced with a copper “plug” which fills the final via structure. Copper Plug formation processes are generally incompatible with the thick-PSPI CPI structures described above. Simultaneous with all of these concerns is the requirement to create a chip-edge crackstop structure that will prevent microcracks from propagating through the dielectric layers of the chip.
More specifically, the dicing operation used to cut a semiconductor wafer into individual chips often induces microcracks in both the semiconductor substrate and the dielectric layers on top. Microcracks occurring in silicon substrates propagate very rapidly and tend to lead to failures that show up in the initial testing described above. Microcracks in dielectric layers propagate more slowly and tend to lead to delayed failures—often after the device is put in service in the field. Failures in the field are particularly expensive and disruptive.